Traditionally, sequential circuits that contain one or more sequential devices, such as flip-flops, am tested by applying one or more test vector sequences to the circuit at its primary inputs and then observing the response at the circuit outputs. The test vectors are generated such that upon application to the circuit, the vectors excite a fault (such as a "stuck-at-zero" or "stuck-at-one" fault) at one or more selected nodes of interest. For example, if a stuck-at-zero fault is present at a selected node, then the test vector sequence causes a logic "1" to be present at the selected node. In this way, a stuck-at-zero fault will manifest itself, causing a logic "0" rather than a logic "1" to appear at the selected node.
Simply exciting the fault condition at each selected node is generally insufficient for testing purposes because the faults at one or more selected nodes may not be observable at the circuit primary outputs. In other words, even though a fault may be excited at a selected node, the signals at the sequential circuit primary outputs may not change in response to the fault. Thus, for proper testing, the sequence of test vectors must excite the fault at each node of interest and must propagate the fault effect to one of the primary outputs of the sequential circuit to allow detection of the fault.
While the traditional test method just described is effective for most sequential circuits, this method does not work well for sequential circuits that contain one or more embedded RAMs. In practice, traditional test techniques have not been effective to propagate those logic values through an embedded RAM that are needed to excite a fault downstream of that RAM. Also, such techniques have not been effective to propagate the fault effect at an upstream node through the embedded RAM to a sequential circuit primary output. As a consequence, most sequential circuits that contain embedded RAMs are tested by excluding each RAM during the test so that the circuit appears purely sequential in nature. The disadvantage of this approach is that the degree of fault coverage, (i.e., the percentage of faults that can be detected) is likely to be low. Excluding the embedded RAMs during circuit testing prevents detection of those faults whose effect must be propagated through an embedded RAM in order to be observed.
Thus there is a need for a technique for testing a RAM-containing sequential circuit that affords high fault coverage.